i ce dice ? : ICE65L04 ultra low - power fpga known good die siliconblue r march 23 , 200 9 ( 1 . 5 . 3 ) preliminary (subject to change) ? 2007 - 2009 by siliconblue technologies corporation . all rights reserved. (1. 5 . 3 , 2 3 - mar - 2009 ) www.siliconbluetech.com preliminary 1 features ? first u ltra low - power programmable logic family specifically designed for hand - held applications and long battery life ? less than 15 a typical standby current ( C u) ; no special power down modes required ? lowest active power consumption of any comparable programmable logic family ? lowest heat dissipation on power - sensitive applications ? known good die (kg d ) ? i deal for system - in - package (sip), stacked - die, or multi - chip module applications ? ideal for chip on board (cob) mounting in low - cost consumer products ? various temperature range, thickness, and delivery method options ? reprogrammable from a variety of sources ? self - loading from secure, internal nonvolatile configuration memory (nvcm) ? superior d esign and intellectual property (ip) protection; no exposed configuration data ? single - chip programmable solution ? low - cost, high - volume configuration source ? self - loading from external, commodity spi serial flash prom ? downloaded by processor using spi - like serial interface ? b uilt on proven, high - volume 65 nm, low - power cmos technology delivering lowest possible power and cost ? up to 200+ mhz internal performance ? flexible programmable logic and programmable interconnect fa bric ? over 3,500 k four - input look - up tables (lut4) and flip - flops ? low - power logic and interconnect ? on - chip, 4kbit ram blocks; 20 per device ? flexible i/o blocks to simplify system interfaces ? 176 programmable i/o pads ? four independently - powered i/o banks support 3.3v, 2.5v, or 1.8v voltage standards ? differential lvds i/o pairs figure 1 : ice65 l04 die photo (magnified) table 1 : ice65 ultra low - power programmable logic family summary ice65l02 ICE65L04 ice65l08 ice65l16 logic cells (lut + flip - flop) 1,792 3,520 7,680 16,896 approximate system gate count 100k 20 0k 400k 800k typical equivalent macrocells 1,400 2, 7 00 6,000 13,000 ram4k memory blocks 16 20 32 96 ram4k ram bits 64k 80k 128k 384k configuration bits ( kbits maximum) 314 kb 533 kb 1,057 kb 2,404 kb typical current at 32.768 khz ( - u ) 8 a 15 a 30 a 75 a maximum programmable i/o pins 128 176 222 384 maximum differential input pairs 16 20 25 54
ice dice?: ICE65L04 die data sheet (1. 5 . 3 , 2 3 - mar - 2009 ) siliconblue technologies corporation 2 preliminary www.siliconbluetech.com overview the siliconblue technologies i ce 65 programmable logic family is specifically designed to deliver the lowest standby and dynamic power consumption of any comparable cpld or fpga device. i ce 65 components are available in two versions. the standard product, designed for cost - sensitive, sing le - program, high - volume applications, provides on - chip, nonvolatile configuration memory (nvcm) to customize the i ce device for a specific application. both the standard version with nvcm memory and t he optional development version without nvcm memory can be self - configured from a program saved in an external commodity spi serial flash prom or downloaded from an external processor over an spi - like serial port . the four i ce components, highlighted in table 1 deliver from approximately 2k to nearly 17 k logic cells and flip - flops while consuming a fraction of the power of comparable programmable logic devices . each i ce device includes between 16 t o 96 ram blocks , each with 4kbits of storage, for on - chip data storage and data buffering. as pictured in figure 2 , e ach i ce device consists of four p rimary architectural elements. ? an array of programmable logic blocks ( plb s ) ? each plb contains eight logic cells (lcs) ; each logic cell consists of ? a fast, four - input look - up table (lut4) capable of implement any combinational logic function of up to four inputs, regardless of complexity ? a d - type flip - flop with an optional clock - enable and set/ reset control ? fast carry logic to accelerate arithmetic functions such as adders, subtracters, comparators, and counters. ? common clock input, clock - enabled input, and optional set/reset control input to plb shared among all eight logic cells ? two - port, 4kbit ram blocks (ram4k) ? 256x16 default configuration; selectable data width using programmable logic resources ? simu ltaneous read and write access; ideal for fifo memory and data buffering applications ? ram c ontents pre - loadable during configuration ? four i/o banks with independent supply voltage, each with multiple programmable input/output (pio) blocks ? programmable inte rconnections between the blocks ? flexible connections between all programmable logic functions ? eight d edicated low - skew, high - fanout clock distribution networks figure 2 : ice65 family architectural features i/o bank 0 i/o bank 2 i/o bank 1 i/o bank 3 plb plb plb plb plb plb plb plb plb plb plb plb plb plb plb programmable interconnect programmable interconnect programmable interconnect 15 a at f 32.768 khz (?u, typical) nvcm plb plb plb 4kbit ram 4kbit ram plb plb plb plb nonvolatile configuration memory ( nvcm) plb plb plb plb jtag spi config four- input look -up table (lut4) carry logic flip- flop with enable and reset controls programmable logic block (plb) 8 logic cells = programmable logic block plb plb plb plb programmable interconnect plb plb ICE65L04
siliconblue siliconblue technologies corporation (1. 5 . 3 , 2 3 - mar - 2009 ) www.siliconbluetech.com preliminary 3 ordering information figure 3 desc ribes the ice65 die - based product ordering codes. figure 3 : ice65 ordering codes logic cells (x1, 000) power consumption configuration memory delivery option wafer/die thickness f = nonvolatile configuration memory (nvcm ) + reprogrammable w = whole wafer, uncut, with wafer map b = whole wafer, sawed, with wafer map , mounted on blue tape t = tape and reel , good die only p = waffle pack, good die only 02 , 04 , 08 , 16 ice 65 l 04 f - l di 310 c w die-based product temperature range c = commercial i = industrial -u = ultra low power (1.0v operation ) -l = low power (1.2v operation ) 040 = 4.0 mil 100 = 10.0 mil 310 = 31.0 mil t p w b yes yes yes 4.0 10.0 31.0 no no no no no yes yes yes yes thick - ness delivery option ice65 devices are available with two power consumption options. standard products ( - l ordering code) have low standby and dynamic power consumption. the - u option specifies the ultra low power version. please consult the die distributor or siliconblue technologies corporation before ordering to verify long - term availabili ty of these die products. specifications discussed herein are subject to change without notice. this product is sold as is and is delivered with no guarantees or warranties, express or implied. functional specifications please refer to the packaged produ ct data sheet found on the siliconblue technologies web site ( www.siliconbluetech.com ) for functional and parametric specifications. the specifications are provided for reference only.
ice dice?: ICE65L04 die data sheet (1. 5 . 3 , 2 3 - mar - 2009 ) siliconblue technologies corporation 4 preliminary www.siliconbluetech.com physical specifications figure 4 shows the physical outlines of ICE65L04 die on a wafer, including pad orientation and physical origin. the bond pad identification and coord inates are provided in table 3 . table 2 lists key physical characteristics of each ICE65L04 die. figure 4 : ICE65L04 die outline dsw_x dsw_y 65 128 190 siliconblue technologies ICE65L04 die i/o bank 0 note: not to scale. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 +y +x i/o bank 3 67 69 71 73 75 i/o bank 2 / spi bank 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 127 130 132 134 136 138 140 142 144 146 i/o bank 1 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 coordinates listed relative to this origin 129 189 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 191 193 195 253 197 199 201 203 205 207 209 211 213 215 217 219 221 223 225 227 229 231 233 235 237 239 241 243 245 247 249 251 192 194 196 198 200 202 204 206 208 210 212 214 216 218 220 222 224 226 228 230 232 234 236 238 240 242 244 246 248 250 252 254 table 2 : ice 65 l04 dice physical specifications feature dimension wafer diameter 300 mm (12 inches) wafer thickness 31 mil , 15 mil, or 10 mil , specified in order code , figure 3 . s tepping i nterval 3,8 7 0 m x 3, 200 scribe width along x - axis (dsw_x) 8 0 m scribe width along y - axis (dsw_y) 160 m bond pad size (min) 61 m x 7 5 m passivation openings (min) 58 m x 72 m minimum bond pad pitch (staggered) 35 m
siliconblue siliconblue technologies corporation (1. 5 . 3 , 2 3 - mar - 2009 ) www.siliconbluetech.com preliminary 5 bond pad listing and coordinates table 3 lists each of the 254 bonding pads on an ICE65L04 device. the pad number begins in the upper left corner of the die, as shown in figure 4 , and increments in a counter - clockwise direction around the perimeter of the die. . each bonding pad is identified. signal names are color - coded by function. i/o pairs are grouped together with a thick surrounding box. these pairs in i/o bank 3 represent an optional differential input or output. in all other banks, these pairs represent an optional differential output. the pad coordinates are measured relative to the origin, in the lower left corner of the die . table 3 : ICE65L04 bond pad listing and coordinates (relative to origin ) pad signal name from origin x (m) y (m) 1 pio3_00/dp00a 129.40 2,687.75 2 pio3_01/dp00b 231.40 2,642.74 3 pio3_02/dp01a 129.40 2,597.75 4 pio3_03/dp01b 231.40 2,552.74 5 gnd 129.40 2,507.75 6 gnd 231.40 2,462.74 7 vccio_3 129.40 2,417.75 8 vccio_3 231.40 2,372.74 9 pio3_04/dp02a 129.40 2,327.75 10 pio3_05/dp02b 231.40 2,292.74 11 pio3_06/dp03a 129.40 2,257.75 12 pio3_07/dp03b 231.40 2,222.74 13 vcc 129.40 2,187.75 14 pio3_08/dp04a 231.40 2,152.74 15 pio3_09/dp04b 129.40 2,117.75 16 pio3_10/dp05a 231.40 2,082.74 17 pio3_11/dp05b 129.40 2,047.75 18 gnd 231.40 2,012.74 19 pio3_12/dp06a 129.40 1,977.75 20 pio3_13/dp06b 231.40 1,942.74 21 gnd 129.40 1,907.75 22 gnd 231.40 1,872.74 23 pio3_1 4 /dp0 7 a 129.40 1,837.75 24 pio3_15 /dp0 7 b 231.40 1,802.74 25 vccio_3 129.40 1,767.75 26 vcc 231.40 1,732.74 27 pio3_ 16 /dp 08a 129.40 1,697.75 28 pio3_ 17 /dp 08 b 231.40 1,662.74 29 pio3_ 18 /dp 09a 129.40 1,627.75 30 gbin 7 /pio3_ 19 /dp 09b 231.40 1,592.74 31 vccio_3 129.40 1,557.75 32 vref 231.40 1,522.74 33 gnd 129.40 1,487.75 34 gbin 6 /pio3_ 20 /dp 10 a 231.40 1,452.74 35 pio3_ 21 /dp 10b 129.40 1,417.75 36 gnd 231.40 1,382.74 37 pio3_ 2 2/ dp 11 a 129.40 1,347.75 38 pio3_ 23 /dp 11b 231.40 1,312.74 pad signal name from origin x (m) y (m) 39 vccio_3 129.40 1,277.75 40 vccio_3 231.40 1,242.74 41 gnd 129.40 1,207.75 42 gnd 231.40 1,172.74 43 pio3_ 24/dp12 a 129.40 1,137.75 44 pio3_ 25 /dp 12 b 231.40 1,102.74 45 gnd 129.40 1,067.75 46 pio3_ 26/dp13 a 231.40 1,032.74 47 pio3_ 27 /dp 13 b 129.40 997.75 48 pio3_ 28/dp14 a 231.40 962.74 49 pio3_ 29 /dp 14b 129.40 927.75 50 pio3_ 30 /dp 15 a 231.40 892.74 51 pio3_ 31 /dp 15b 129.40 857.75 52 vcc 231.40 822.74 53 pio3_ 32 /dp 16 a 129.40 787.75 54 pio3_ 33 /dp 16 b 231.40 752.74 55 vccio_3 129.40 717.75 56 vccio_3 231.40 682.74 57 gnd 129.40 637.75 58 gnd 231.40 592.74 59 pio3_ 34 /dp 17 a 129.40 547.75 60 pio3_ 35 /dp 17 b 231.40 502.74 61 pio3_ 36 /dp 18a 129.40 457.75 62 pio3_ 37 /dp 18b 231.40 412.74 63 pio3_ 38 /dp 19 a 129.40 367.75 64 pio3_ 39 /dp 19b 231.40 322.74 65 pio2_00 545.00 139.20 66 pio2_01 595.00 37.20 67 pio2_02 645.00 139.20 68 gnd 695.00 37.20 69 pio2_03 745.00 139.20 70 pio2_04 795.00 37.20 71 pio2_05 845.00 139.20 72 pio2_06 895.00 37.20 73 pio2_07 930.00 139.20 74 pio2_08 965.00 37.20 75 vccio_2 1,000.00 139.20 76 pio2_09 1,035.00 37.20
ice dice?: ICE65L04 die data sheet (1. 5 . 3 , 2 3 - mar - 2009 ) siliconblue technologies corporation 6 preliminary www.siliconbluetech.com pad signal name from origin x (m) y (m) 77 pio2_10 1,070.00 139.20 78 gnd 1,105.00 37.20 79 pio2_11 1,140.00 139.20 80 pio2_12 1,175.00 37.20 81 pio2_1 3 1,210.00 139.20 82 pio2_1 4 1,245.00 37.20 83 pio2_1 5 1,280.00 139.20 84 pio2_ 16 1,315.00 37.20 85 pio2_ 17 1,350.00 139.20 86 pio2_18 1,385.00 37.20 87 gnd 1,420.00 139.20 88 pio2_ 19 1,455.00 37.20 89 pio2_ 20 1,490.00 139.20 90 vcc 1,525.00 37.20 91 pio2_ 21 1,560.00 139.20 92 pio2_ 22 1,595.00 37.20 93 gbin 5 /pio2_ 23 1,630.00 139.20 94 gbin 4 /pio2_2 4 1,665.00 37.20 95 pio2_2 5 1,700.00 139.20 96 vccio_2 1,735.00 37.20 97 pio2_ 26 1,770.00 139.20 98 pio2_ 27 1,805.00 37.20 99 gnd 1,840.00 139.20 100 pio2_ 28 1,875.00 37.20 101 pio2_ 29 1,910.00 139.20 102 pio2_ 30 1,945.00 37.20 103 pio2_ 31 1,980.00 139.20 104 pio2_ 32 2,015.00 37.20 105 pio2_ 33 2,050.00 139.20 106 pio2_ 34 2,085.00 37.20 107 pio2_ 35 2,120.00 139.20 108 vcc 2,155.00 37.20 109 vcc 2,190.00 139.20 110 pio2_ 36 2,225.00 37.20 111 pio2_ 37 2,260.00 139.20 112 vccio_2 2,295.00 37.20 113 pio2_ 38 2,330.00 139.20 114 gnd 2,365.00 37.20 115 pio2_ 39 2,400.00 139.20 116 pio2_ 40 2,435.00 37.20 117 pio2_ 41 2,470.00 139.20 118 pio2_ 42 /cbsel0 2,505.00 37.20 119 pio2_ 43 /cbsel1 2,540.00 139.20 120 cdone 2,575.00 37.20 121 creset_b 2,625.00 139.20 122 pios_ 00 /spi_so 2,690.00 37.20 123 pios_ 01 /spi_si 2,740.00 139.20 pad signal name from origin x (m) y (m) 124 gnd 2,790.00 37.20 125 pios_ 02 /spi_sck 2,840.00 139.20 126 pios_ 03 /spi_ss_b 2,890.00 37.20 127 spi_vcc 2,990.00 37.20 128 tdi 3,610.80 342.00 129 tms 3,712.80 392.00 130 tck 3,610.80 442.00 131 tdo 3,712.80 492.00 132 trst_b 3,610.80 542.00 133 pio1_ 00 3,712.80 592.00 134 pio1_01 3,610.80 642.00 135 pio1_02 3,712.80 692.00 136 pio1_03 3,610.80 727.00 137 gnd 3,712.80 762.00 138 gnd 3,610.80 797.00 139 pio1_04 3,712.80 832.00 140 pio1_05 3,610.80 867.00 141 vccio_1 3,712.80 902.00 142 vccio_1 3,610.80 937.00 143 pio1_06 3,712.80 972.00 144 pio1_07 3,610.80 1,007.00 145 pio1_08 3,712.80 1,042.00 146 pio1_09 3,610.80 1,077.00 147 pio1_ 10 3,712.80 1,112.00 148 vcc 3,610.80 1,147.00 149 vcc 3,712.80 1,182.00 150 pio1_11 3,610.80 1,217.00 151 pio1_ 12 3,712.80 1,252.00 152 pio1_ 13 3,610.80 1,287.00 153 pio1_ 14 3,712.80 1,322.00 154 pio1_ 15 3,610.80 1,357.00 155 pio1_ 16 3,712.80 1,392.00 156 pio1_ 17 3,610.80 1,427.00 157 gnd 3,712.80 1,462.00 158 gnd 3,610.80 1,497.00 159 pio1_ 18 3,712.80 1,532.00 160 gbin3/pio1_ 19 3,610.80 1,567.00 161 gbin2/pio1_ 20 3,712.80 1,602.00 162 pio1_ 21 3,610.80 1,637.00 163 vccio_1 3,712.80 1,672.00 164 vccio_1 3,610.80 1,707.00 165 pio1_ 22 3,712.80 1,742.00 166 pio1_ 23 3,610.80 1,777.00 167 pio1_ 24 3,712.80 1,812.00 168 pio1_ 25 3,610.80 1,847.00 169 pio1_ 26 3,712.80 1,882.00 170 pio1_ 27 3,610.80 1,917.00
siliconblue siliconblue technologies corporation (1. 5 . 3 , 2 3 - mar - 2009 ) www.siliconbluetech.com preliminary 7 pad signal name from origin x (m) y (m) 171 gnd 3,712.80 1,952.00 172 gnd 3,610.80 1,987.00 173 pio1_ 28 3,712.80 2,022.00 174 pio1_ 29 3,610.80 2,057.00 175 pio1_ 30 3,712.80 2,092.00 176 pio1_ 31 3,610.80 2,127.00 177 vcc 3,712.80 2,162.00 178 vcc 3,610.80 2,197.00 179 pio1_ 32 3,712.80 2,232.00 180 pio1_ 33 3,610.80 2,267.00 181 vccio_1 3,712.80 2,302.00 182 vccio_1 3,610.80 2,337.00 183 pio1_ 34 3,712.80 2,377.00 184 pio1_ 35 3,610.80 2,427.00 185 gnd 3,712.80 2,477.00 186 pio1_ 36 3,610.80 2,527.00 187 pio1_37 3,712.80 2,577.00 188 pio1_ 38 3,610.80 2,627.00 189 pio1_ 39 3,712.80 2,677.00 190 vpp_ 2v5 3,610.80 2,739.68 191 vpp_fast 3,097.00 2,962.80 192 vcc 2,997.00 2,860.80 193 vcc 2,947.00 2,962.80 194 pio0_ 00 2,897.00 2,860.80 195 pio0_ 01 2,847.00 2,962.80 196 pio0_ 02 2,797.00 2,860.80 197 pio0_ 03 2,747.00 2,962.80 198 pio0_ 04 2,697.00 2,860.80 199 pio0_ 05 2,647.00 2,962.80 200 pio0_ 06 2,612.00 2,860.80 201 pio0_ 07 2,577.00 2,962.80 202 gnd 2,542.00 2,860.80 203 gnd 2,507.00 2,962.80 204 pio0_ 08 2,472.00 2,860.80 205 pio0_ 09 2,437.00 2,962.80 206 pio0_ 10 2,402.00 2,860.80 207 pio0_ 11 2,367.00 2,962.80 208 pio0_ 12 2,332.00 2,860.80 209 pio0_ 13 2,297.00 2,962.80 210 pio0_ 14 2,262.00 2,860.80 211 pio0_ 15 2,227.00 2,962.80 212 vccio_0 2,192.00 2,860.80 213 vccio_0 2,157.00 2,962.80 214 pio0_ 16 2,122.00 2,860.80 215 pio0_ 17 2,087.00 2,962.80 pad signal name from origin x (m) y (m) 216 pio0_ 18 2,052.00 2,860.80 217 pio0_ 19 2,017.00 2,962.80 218 pio0_ 20 1,982.00 2,860.80 219 pio0_ 21 1,947.00 2,962.80 220 pio0_ 22 1,912.00 2,860.80 221 gbin1/pio0_ 23 1,877.00 2,962.80 222 gnd 1,842.00 2,860.80 223 gnd 1,807.00 2,962.80 224 gbin0/pio0_ 24 1,772.00 2,860.80 225 pio0_ 25 1,737.00 2,962.80 226 pio0_ 26 1,702.00 2,860.80 227 pio0_ 27 1,667.00 2,962.80 228 vcc 1,632.00 2,860.80 229 vcc 1,597.00 2,962.80 230 pio0_ 28 1,562.00 2,860.80 231 pio0_ 29 1,527.00 2,962.80 232 pio0_ 30 1,492.00 2,860.80 233 pio0_ 31 1,457.00 2,962.80 234 gnd 1,422.00 2,860.80 235 gnd 1,387.00 2,962.80 236 pio0_ 32 1,352.00 2,860.80 237 pio0_ 33 1,317.00 2,962.80 238 pio0_ 34 1,282.00 2,860.80 239 pio0_ 35 1,247.00 2,962.80 240 pio0_ 36 1,212.00 2,860.80 241 vccio_0 1,177.00 2,962.80 242 vccio_0 1,142.00 2,860.80 243 pio0_ 37 1,107.00 2,962.80 244 pio0_ 38 1,072.00 2,860.80 245 pio0_ 39 1,037.00 2,962.80 246 pio0_ 40 1,002.00 2,860.80 247 pio0_ 41 967.00 2,962.80 248 pio0_ 42 917.00 2,860.80 249 gnd 867.00 2,962.80 250 pio0_ 43 817.00 2,860.80 251 pio0_ 44 767.00 2,962.80 252 pio0_ 45 717.00 2,860.80 253 pio0_ 46 667.00 2,962.80 254 pio0_ 47 617.00 2,860.80
ice dice?: ICE65L04 die data sheet (1. 5 . 3 , 2 3 - mar - 2009 ) siliconblue technologies corporation 8 preliminary www.siliconbluetech.com die testing procedures siliconblue technologies die products are tested to ensure product functionality in our standard package. each die has gone through wafer probe test of various functional and parametric conditions. siliconblue technologies retains a wafer map of each wafer as part of the probe records, along with a lot summary of wafer yields for each lot probed. siliconblue technologies reserves the r ight to change the probe program at any time for continuous product improvement . die users may experience differences in performance relative to siliconblue technologies data sheets. this is due to differences in package capacitance, inductance, resistan ce, and trace length. product reliability monitors reliability of all packaged products is monitored by ongoing qra reliability evaluations. from these evaluations, samples are subjected to a battery of tests know n as accelerated life and envi ronmental stress tests. during these tests, devices are stressed for many hours under conditions designed to simulate years of normal field use. a summary of these product family evaluations is published on a regular basis. storage requirements siliconblue technolo gies die products are packaged in a cleanroom environment for shipping. upon receipt, transfer the die or wafers to a similar environment for stor age. siliconblue technologies recommends that the die or wafers be maintai ned in a filtered nitrogen atmo sph ere until removed for assembly. the moisture content of the storage facility should be maintained at 30% 10% relative humidity. esd damage precautions are necessary during handling. the die must be in an esd - protected environment at all times for inspecti on and assembly. siliconblue r siliconblue technologies corporation 3255 scott blvd. building 7, suite 101 santa clara, california 95054 united states of america tel: +1 408 - 530 - 8800 fax: +1 408 - 530 - 0177 www.siliconbluetech.com
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